1 commercial temperature range idt23s08t 2.5v zero delay clock multiplier november 2003 2003 integrated device technology, inc. dsc - 6510/4 c commercial temperature range the idt logo is a registered trademark of integrated device technology, inc. features: ? phase-lock loop clock distribution for applications ranging from 10mhz to 133mhz operating frequency ? distributes one clock input to two banks of four outputs ? separate output enable for each output bank ? external feedback (fbk) pin is used to synchronize the outputs to the clock input ? output skew <200 ps ? low jitter <200 ps cycle-to-cycle ? 1/2x, 1x, 2x, 4x output options (see table): ? IDT23S08T-1 1x ? idt23s08t-2 1x, 2x ? idt23s08t-3 2x, 4x ? idt23s08t-4 2x ? idt23s08t-5 1/2x ? no external rc network required ? operates at 2.5v v dd ? spread spectrum compatible ? available in soic package functional block diagram description: the idt23s08t is a high-speed phase-lock loop (pll) clock multiplier. it is designed to address high-speed clock distribution and multiplication applica- tions. the zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133mhz. the idt23s08t has two banks of four outputs each that are controlled via two select addresses. by proper selection of input addresses, both banks can be put in tri-state mode. in test mode, the pll is turned off, and the input clock directly drives the outputs for system testing purposes. in the absence of an input clock, the idt23s08t enters power down. in this mode, the device will draw less than 12a, and the outputs are tri-stated. the idt23s08t is available in six unique configurations for both pre- scaling and multiplication of the input ref clock. (see available options table.) the pll is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. the idt23s08t is characterized for commercial operation. idt23s08t advance information 2.5v zero delay clock multiplier, spread spectrum compatible pll s1 2 14 15 3 clka1 clka2 clka3 clka4 6 10 11 clkb1 clkb2 clkb3 clkb4 9 fbk 16 (-3, -4) 2 control logic 7 8 1 ref s2 (-2, -3) 2 (-5) 2
2 commercial temperature range idt23s08t 2.5v zero delay clock multiplier pin configuration soic top view ref clka1 s2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 clka2 gnd clkb1 fbk clka4 gnd s1 v dd v dd clkb2 clkb3 clkb4 clka3 symbol rating max. unit v dd supply voltage range ?0.5 to +4.6 v v i (2) input voltage range (ref) ?0.5 to +5.5 v v i input voltage range ?0.5 to v (except ref) v dd +0.5 i ik (v i < 0) input clamp current ?50 ma i o continuous output current 50 ma (v o = 0 to v dd ) v dd or gnd continuous current 100 ma t a = 55c maximum power dissipation 0.7 w (in still air) (3) t stg storage temperature range ?65 to +150 c operating commercial temperature 0 to +70 c temperature range notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. the maximum package power dissipation is calculated using a junction temperature of 150 c and a board trace length of 750 mils. applications: ? sdram ? telecom ? datacom ? pc motherboards/workstations ? critical path delay designs pin number functional description ref (1) 1 input reference clock, 3.3v tolerant input clka1 (2) 2 clock output for bank a clka2 (2) 3 clock output for bank a v dd 4 2.5v supply gnd 5 ground clkb1 (2) 6 clock output for bank b clkb2 (2) 7 clock output for bank b s2 (3) 8 select input, bit 2 s1 (3) 9 select input, bit 1 clkb3 (2) 10 clock output for bank b clkb4 (2) 11 clock output for bank b gnd 12 ground v dd 13 2.5v supply clka3 (2) 14 clock output for bank a clka4 (2) 15 clock output for bank a fbk 16 pll feedback input notes: 1. weak pull down. 2. weak pull down on all outputs. 3. weak pull ups on these inputs. pin description absolute maximum ratings (1)
3 commercial temperature range idt23s08t 2.5v zero delay clock multiplier s2 s1 clk a clk b output source pll shut down l l tri-state tri-state pll y l h driven tri-state pll n h l driven driven ref y h h driven driven pll n function table (1) select input decoding note: 1. h = high voltage level l = low voltage level spread spectrum compatible many systems being designed now use a technology called spread spectrum frequency timing generation. this product is designed not to filter off the spread spectrum feature of the reference input, assuming it exists. when a zero delay buffer is not designed to pass t he spread spectrum feature through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization. device feedback from bank a frequency bank b frequency IDT23S08T-1 bank a or bank b reference reference idt23s08t-2 (1) bank a reference reference/2 idt23s08t-2 (1) bank b 2 x reference reference idt23s08t-3 (1) bank a 2 x reference reference or reference (2) idt23s08t-3 (1) bank b 4 x reference 2 x reference idt23s08t-4 (1) bank a or bank b 2 x reference 2 x reference idt23s08t-5 (1) bank a or bank b reference/2 reference/2 notes: 1. contact factory for availability. 2. output phase is indeterminant (0 or 180 from input clock). available options for idt23s08t zero delay and skew control to close the feedback loop of the idt23s08t, the fbk pin can be driven from any of the eight available output pins. the output driving the fbk pin will be driving a total load of 7pf plus any additional load that it drives. the relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. for applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. ensure the outputs are loaded equally, for zero output-output skew. note: 1. applies to both ref and fbk. symbol parameter test conditions min. max. unit v dd supply voltage 2.3 2.7 v t a operating temperature (ambient temperature) 0 70 c c l load capacitance from 10mhz to 133mhz ? 15 pf c in input capacitance (1) ?7pf operating conditions
4 commercial temperature range idt23s08t 2.5v zero delay clock multiplier dc electrical characteristics symbol parameter conditions min. typ. (1) max. unit v il input low voltage level ? ? 0.7 v v ih input high voltage level 1.7 ? ? v i il input low current v in = 0v ? ? 50 a i ih input high current v in = v dd ? ? 100 a v ol output low voltage i ol = 8ma ? ? 0.3 v v oh output high voltage i oh = -8ma 2 ? ? v i dd_pd power down current ref = 0mhz (s2 = s1 = h) ? ? 12 a 100mhz clka ? ? 45 i dd supply current unloaded outputs 66mhz clka ? ? 32 ma select inputs at v dd or gnd 33mhz clka ? ? 18 switching characteristics symbol parameter conditions min. typ. max. unit t 1 output frequency 15pf load 10 ? 133.3 m h z duty cycle = t 2 t 1 measured at v dd /2, f out = 66.66mhz, 15pf load 40 50 60 % t 3 rise time measured between 0.7v and 1.7v, 15pf load ? ? 2.5 ns t 4 fall time measured between 0.7v and 1.7v, 15pf load ? ? 2.5 ns t 5 output to output skew on same bank all outputs equally loaded ? ? 200 ps (-1, -2, -3, -4, -5) output bank a to output bank b (-1, -4, -5) all outputs equally loaded ? ? 200 ps output bank a to output bank b skew (-2, -3) all outputs equally loaded ? ? 400 ps t 6 delay, ref rising edge to fbk rising edge measured at v dd /2 ? 0 350 ps t 7 device to device skew measured at v dd /2 on the fbk pins of devices ? 0 700 ps t j cycle to cycle jitter (-1, -4, -5) measured at 66.67 mhz, loaded outputs, 15pf load ? ? 200 ps measured at 133.3 mhz, loaded outputs, 15pf load ? ? 200 tj cycle to cycle jitter (-2, -3) measured at 66.67 mhz, loaded outputs, 15pf load ? ? 400 ps t lock pll lock time stable power supply, valid clocks presented ? ? 1 ms on ref and fbk pins
5 commercial temperature range idt23s08t 2.5v zero delay clock multiplier output t5 output v dd /2 v dd /2 input t6 v dd /2 fbk v dd /2 t7 v dd /2 fbk, device 2 v dd /2 fbk, device 1 v dd /2 t2 t1 1.7v 0.7v t3 t4 0.7v 2.5v 0v 1.7v output v dd /2 v dd /2 switching waveforms duty cycle timing all outputs rise/fall time output to output skew input to output propagation delay device to device skew test circuit test circuit for all parameters v dd outputs clk out c load v dd gnd gnd 0.1 f 0.1 f
6 commercial temperature range idt23s08t 2.5v zero delay clock multiplier ordering information ordering code package type operating range IDT23S08T-1dc 16-pin soic commercial idt23s08t-2dc (1) 16-pin soic commercial idt23s08t-3dc (1) 16-pin soic commercial idt23s08t-4dc (1) 16-pin soic commercial idt23s08t-5dc (1) 16-pin soic commercial corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com idt xxxxx xx x package process device type blank 23s08t-1 23s08t-2 23s08t-3 23s08t-4 23s08t-5 commercial (0 o c to +70 o c) 2.5v zero delay clock buffer, spread spectrum compatible dc small outline note: 1. contact factory for availability.
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